Technical Field
The present disclosure is related to the field of integrated circuit dies. The present disclosure is related more particularly to integrated circuits having higher voltage range operations.
Description of the Related Art
As integrated circuit die technology advances to further and further technology nodes, the gate oxide thickness of MOS transistors continues to shrink. As the gate oxide thickness of MOS transistors shrinks, so does the maximum voltage which can appear across the terminals of the transistors. At or below the 32 nm technology node, CMOS transistors typically cannot tolerate greater than 2 V across any two of the terminals, except bulk. If too high a voltage is applied between the terminals of CMOS transistor, the functionality of the transistor can be destroyed. Various protection schemes are commonly implemented within circuits in order to avoid the possibility that the voltage overload occurs across the terminals of sensitive CMOS transistors.
FIG. 1 is a schematic diagram of a known inverter circuit implemented at the 32 nm node or smaller in bulk technologies, as well as at the 28 nm FDSOI technology node. The inverter circuit includes a PMOS transistor P1 and an NMOS transistor N1. The PMOS transistor P1 has a source terminal and a bulk terminal connected to VDD. The NMOS transistor N1 has a source and a bulk terminal connected to ground. The drains of the transistors N1 and P1 are connected to each other at the output Out of the circuit. Due to the thinness of the gate oxide of the transistors N1 and P1, it is important to protect the transistors P1 and N1 from receiving a gate voltage higher than its stress limits. To this end, the inverter 20 includes a first protection circuit 22a and a second protection circuit 22b. The first protection circuit 22a is coupled between the input In of the inverter and the gate of the transistor P1. The protection circuit 22a includes a PMOS transistor P2 and a PMOS transistor P3. The gate of the PMOS transistor P2 is coupled to the input In. The source of the transistor P2 is coupled to a reference voltage Vref. The level of Vref is lower than or equal to the stress limit of the MOS devices. The drain of the transistor P2 is coupled to the gate of the transistor P1. The gate of the transistor P3 is coupled to the reference voltage Vref. The drain of the transistor P3 is coupled to the input In. The source of the transistor P3 is coupled to the gate of the transistor P1.
The second protection circuit 22b is similar to the first protection circuit 22a. The second protection circuit 22b is coupled between the input In of the inverter 20 and the gate of the transistor N1. The protection circuit 22b includes an NMOS transistor N2 and an NMOS transistor N3. The gate of the NMOS transistor N2 is coupled to the input In. The source of the transistor N2 is coupled to a reference voltage Vref. The drain of the transistor N2 is coupled to the gate of the transistor N1. The gate of the transistor N3 is coupled to the reference voltage Vref. The drain of the transistor N3 is coupled to the input In. The source of the transistor N3 is coupled to the gate of the transistor N1. The protection circuits 22a, 22b help to limit the gate voltage on the transistors P1 and N1 to the stress ceiling of the device.
When the input In is high the transistor P2 is turned off. The transistor P3 is conducting because the gate of the transistor P3 is tied to the lower reference voltage. The gate of the transistor P1 therefore receives the high voltage from the input In and is rendered non-conducting. But because the transistor P1 is not conducting, the output Out is blocked from the voltage VDD. While the input In is high, the transistor N2 is rendered conducting. The Vref is therefore applied to the gate of the transistor N1. The transistor N1 is therefore conducting. The output Out is connected to the ground voltage GND. When the input In is low, the transistor N2 is turned off, thereby shielding the transistor N1 from the high reference voltage. The transistor N3 is conducting and the gate of the transistor N1 receives the low voltage of In on its gate terminal. The transistor N1 is therefore turned off and the output Out is disconnected from ground. While the input In is low, the transistor P2 is turned on. The gate of the transistor P1 receives the Vref through the transistor P2. The Vref for the P-channel transistors may or may not be the same as the Vref for the N-channel transistors. Thus one may be low Vref and the other high Vref. The protection circuit 22a ensures that the gate of the transistor P1 does not receive a voltage lower than the low reference voltage. The protection circuit 22b ensures that the gate of the transistor N1 does not receive a voltage higher than the high reference voltage.
FIG. 2 is a schematic diagram of a known inverter 20 implemented in a circuit in which a supply voltage VDD is equal to or higher than the stress limit of the MOS devices, e.g. 3.3 V. The known inverter 20 FIG. 2 is essentially identical to the inverter 20 of FIG. 1 except that the PMOS transistor P4 is coupled between the transistor P1 and the output Out. An NMOS transistor N4 is coupled between the transistor N1 and the output Out. The transistor P4 receives on its gate the low reference voltage. The transistor N4 receives on its gate the high reference voltage. The transistors P4 and N4 are always on.
The inverters of FIGS. 1 and 2 have the drawback that they must be protected from high voltages by the protection circuits 22a, 22b. Protection circuits 22a, 22b introduce four additional transistors into the inverter 20. Thus the inverters of FIGS. 1 and 2 consume a large amount of area of the semiconductor substrate in order to accommodate the additional transistors of the protection circuits 22a, 22b. Even with the presence of these two protection circuits 22a, 22b, it is still possible for the transistors P1 and N1 to be damaged by excessive gate voltages when spikes appear in the prior art supply voltage.